1. Field of the Invention
The present invention relates to a voltage dropping circuit for a semiconductor device, and more particularly, it relates to a voltage dropping circuit with which power consumption during a standby time can be reduced.
2. Description of the Related Art
In recent years, semiconductor integrated circuits have been increasingly miniaturized. In particular, this tendency is most noticeable in dynamic RAMs. With the miniaturization of transistors, their supply voltage must be reduced for various reasons, such as lifetime shortening of transistors caused by hot electrons. For example, the supply voltage for transistors having a 0.6 .mu.m gate length must be 4 V or less (e.g., 3.3 V),in general, while the supply voltage which has conventionally been widely used for ICs is 5 V. Consequently, an internal voltage dropping circuit has been used in ICs so that the supply voltage from outside is reduced from 5 V to 3.3 V to be applied to transistors inside.
FIG. 5 is a circuit diagram showing the constitution of a conventional (1/2) V.sub.CC voltage generating circuit as the internal voltage dropping circuit for a semiconductor device.
As shown in FIG. 5, the conventional (1/2) V.sub.CC voltage generating circuit for a semiconductor device is composed of an output transistor control unit 1 and an output transistor unit 2. The output transistor control unit 1 includes two resistors 1a and 1b for dividing a V.sub.CC supply voltage, an n-channel FET 1c and a p-channel FET 1d which are connected therebetween. A voltage increase control terminal 1e outputs a reference voltage which is higher than half the V.sub.CC supply voltage ((1/2) V.sub.CC voltage) by the pinch-off voltage of the FET 1c, while a voltage decrease control terminal 1f outputs a reference voltage which is lower than the (1/2) V.sub.CC voltage by the pinch-off voltage of the FET 1d.
The output transistor unit 2 includes an n-channel FET 2a which is connected between the V.sub.CC power supply and a (1/2) V.sub.CC power supply terminal 3 and a p-channel FET 2b which is connected between the (1/2) V.sub.CC power supply terminal 3 and ground. The reference voltages from the voltage increase control terminal 1e and voltage decrease control terminal 1f are applied to the gates of the FETs 2a and 2b, respectively. When the actual voltage at the (1/2) V.sub.CC power supply terminal 3 becomes lower than the (1/2) V.sub.CC voltage, the FET 2a is activated. In contrast, when the actual voltage at the (1/2) V.sub.CC power supply terminal 3 exceeds the (1/2) V.sub.CC voltage, the FET 2b is activated, thus maintaining the (1/2) V.sub.CC voltage supplied from the (1/2) V.sub.CC power supply terminal 3.
The foregoing conventional (1/2) V.sub.CC voltage generating circuit is designed so that the output transistor control unit 1 always allows the passage of driving current therethrough. However, it has been desired particularly in recent years to minimize the power consumption of semiconductor devices on standby, because of their battery driving and for other reasons.
The conventional (1/2) V.sub.CC voltage generating circuit is therefore disadvantageous in that the presence of driving current in the output transistor control unit 1 prevents the power consumption of a semiconductor device from decreasing during a standby time.
An application of the (1/2) V.sub.CC voltage generating circuit to DRAMs as semiconductor devices is disclosed in Jun. 7th, 1990 IEEE Symposium on VLSI Circuits, A 1.5 V Circuit Technology for 64 Mb DRAMs, pp 17-18, which shows a schematic view of the conventional (1/2) V.sub.CC voltage generating circuit in FIG. 15 thereof.